To Copy or Not to Copy : A Compile - Time Technique for Assessing

In recent years, loop tiling has become an increasingly popular technique for increasing cache eeectiveness. This is accomplished by transforming a loop nest so that the temporal and spatial locality can be better exploited for a given cache size. However, this optimization only targets the reduction of capacity misses. As recently demonstrated by several groups of researchers, connict misses can still preclude eeective cache utilization. Moreover, the severity of cache connicts can vary greatly with slight variations in problem size and starting addresses, making performance dif-cult to even predict, let alone optimize. To reduce connict misses, data copying has been proposed. With this technique, data layout in cache is adjusted by copying array tiles to temporary arrays that exhibit better cache behavior. Although copying has been proposed as the panacea to the problem of cache connicts, this solution experiences a cost proportional to the amount of data being copied. To date, there has been no discussion regarding either this tradeoo or the problem of determining what and when to copy. In this paper, we present a compile-time technique for making this determination , and present a selective copying strategy based on this methodology. Preliminary experimental results demonstrate that, because of the sensitivity of cache connicts to small changes in problem size and base addresses, selective copying can lead to better overall performance than either no copying, complete copying or manually applied heuristics.